A current trend is that the thickness of the semiconductor layer in typical semiconductor-on-insulator (SOI) substrates is decreasing for planar transistors as the technology generations change (e.g., 130 nm to 90 nm to 65 nm technology generation). Currently, the typical thickness of the active region for a planar transistor fabricated using an SOI structutre is about 400 angstroms, and is expected to become smaller in future technology generations.
As shown in FIG. 1, a multiple-gate transistor 20 (e.g., FinFET) typically has a vertical semiconductor fin 22. The vertical semiconductor fin 22 is also known as the active region. The gate dielectric 24 and gate electrode 26 cover a large portion or a majority of the surface of the active region 22 at the channel region because most of the current is conducted along the sidewalls. Thus, generally, a taller fin 22 is better for conducting larger currents, and the vertical fin structure allows for more gate electrode area for better control of the larger currents. The fin height hf in a multiple-gate transistor 20 is preferably greater than the fin width wf. When a semiconductor fin 22 is fabricated from an SOI structure, the fin height hf is typically approximately equal to the thickness of the semiconductor layer of the SOI structure (see e.g., FIG. 1).
It is desired to have FinFET transistor co-existing on a same chip as conventional planar transistors for certain applications. But such desire to have planar transistors and multiple-gate transistors co-existing on a same chip presents unique problems because the active regions for the planar transistors are decreasing and the active regions (fins) for the multiple-gate transistors are desired to be taller. Thus, a need exists for methods and structures of providing planar transistors and multiple-gate transistors on a same chip, e.g., on SOI substrate structures.